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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) and xdcp are trademarks owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners dual, 256-tap, low voltage digitally controlled potentiometer (xdcp?) isl23325 the isl23325 is a volatile, low voltage, low noise, low power, 256-tap, dual digitally controlled potentiometer (dcp) with an i 2 c bus? interface. it integrates two dcp cores, wiper switches and control logic on a monolithic cmos integrated circuit. each digitally controlled potentiometer is implemented with a combination of resistor elements and cmos switches. the position of the wipers are controlled by the user through the i 2 c bus interface. each potentiometer has an associated volatile wiper register (wri, i = 0, 1) that can be directly written to and read by the user. the contents of the wri controls the position of the wiper. when powered on , the wiper of each dcp will always commence at mid-scale (128 tap position). the low voltage, low power consumption, and small package of the isl23325 make it an ideal choice for use in battery operated equipment. in addition, the isl23325 has a v logic pin allowing down to 1.2v bus operation, independent from the v cc value. this allows for low logic levels to be connected directly to the isl23325 with out passing through a voltage level shifter. the dcp can be used as a three- terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. applications ? power supply margining ? trimming sensor circuits ? gain adjustment in battery powered instruments ? rf power amplifier bias compensation features ? two potentiometers per package ? 256 resistor taps ?10k ? 50k ? or 100k ? total resistance ?i 2 c serial interface - no additional level translator for low bus supply - three address pins allow up to eight devices per bus ? maximum supply current wi thout serial bus activity (standby) - 3a @ v cc and v logic = 5v - 1.7a @ v cc and v logic = 1.7v ?shutdown mode - forces the dcp into an end-to-end open circuit and rwi is connected to rli internally - reduces power consumption by disconnecting the dcp resistor from the circuit ?power supply -v cc = 1.7v to 5.5v analog power supply -v logic = 1.2v to 5.5v i 2 c bus/logic power supply ? wiper resistance: 70 ? typical @ v cc = 3.3v ? power-on preset to mid-scale (128 tap position) ? extended industrial temperature range: -40 c to +125 c ? 14 ld tssop or 16 ld tqfn packages ? pb-free (rohs compliant) figure 1. forward and back ward resistance vs tap position, 10k ? dcp figure 2. v ref adjustment 0 2000 4000 6000 8000 10000 tap position (decimal) resistance ( ? ) 0 64 128 192 256 v ref_m isl28114 1 dcp of isl23325 + - v ref rl1 rw1 rh1 june 21, 2011 fn7870.0
isl23325 2 fn7870.0 june 21, 2011 block diagram power up interface , control and status logic i/o block v cc gnd scl sda a0 a1 rh0 rl0 rw0 rh1 rl1 rw1 wr0 volatile register and wiper control circuitry wr1 volatile register and wiper control circuitry a2 v logic level shifter pin configurations isl23325 (14 ld tssop) top view isl23325 (16 ld tqfn) top view sda v logic a0 v cc scl gnd rl1 rw1 rh1 a1 rl0 a2 rh0 rw0 1 2 3 4 5 6 7 14 13 12 11 10 9 8 a2 v logic rh1 gnd nc rl1 rw1 v cc a1 rw0 scl rh0 rl0 sda a0 1 3 4 15 16 14 13 2 12 10 9 11 6 5 7 8 gnd pin descriptions tssop tqfn symbol description 1 6, 15 gnd ground pin 216v logic i 2 c bus/logic supply. range 1.2v to 5.5v 3 1 sda logic pin - serial bus data input/open drain output 4 2 scl logic pin - serial bus clock input 5 3 a0 logic pin - hardwire slave address pin for i 2 c serial bus. range: v logic or gnd 6 4 a1 logic pin - hardwire slave address pin for i 2 c serial bus. range: v logic or gnd 7 5 a2 logic pin - hardwire slave address pin for i 2 c serial bus. range: v logic or gnd 8 8 rl1 dcp1 ?low? terminal 9 9 rw1 dcp1 wiper terminal 10 10 rh1 dcp1 ?high? terminal 11 11 rh0 dcp0 ?high? terminal 12 12 rw0 dcp0 wiper terminal 13 13 rl0 dcp0 ?low? terminal 14 14 v cc analog power supply. range 1.7v to 5.5v 7ncnot connected
isl23325 3 fn7870.0 june 21, 2011 ordering information part number (note 5) part marking resistance option (k ? ) temp range (c) package (pb-free) pkg. dwg. # isl23325tfvz (notes 1, 3) 23325 tfvz 100 -40 to +125 14 ld tssop m14.173 isl23325ufvz (notes 1, 3) 23325 ufvz 50 -40 to +125 14 ld tssop m14.173 isl23325wfvz (notes 1, 3) 23325 wfvz 10 -40 to +125 14 ld tssop m14.173 isl23325tfruz-t7a (notes 2, 4) gbf 100 -40 to +125 16 ld 2.6x1.8 tqfn l16.2.6x1.8a isl23325tfruz-tk (notes 2, 4) gbf 100 -40 to +125 16 ld 2.6x1.8 tqfn l16.2.6x1.8a ISL23325UFRUZ-T7A (notes 2, 4) gbe 50 -40 to +125 16 ld 2.6x1.8 tqfn l16.2.6x1.8a isl23325ufruz-tk (notes 2, 4) gbe 50 -40 to +125 16 ld 2.6x1.8 tqfn l16.2.6x1.8a isl23325wfruz-t7a (notes 2, 4) gbd 10 -40 to +125 16 ld 2.6x1.8 tqfn l16.2.6x1.8a isl23325wfruz-tk (notes 2, 4) gbd 10 -40 to +125 16 ld 2.6x1.8 tqfn l16.2.6x1.8a notes: 1. add ?-tk? suffix for 1k unit or ?-t7a? suffix for 250 unit tape and reel options . please refer to tb347 for details on reel specifications. 2. please refer to tb347 for details on reel specifications. 3. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 4. these intersil pb-free plastic packaged products employ special pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free pr oducts are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 5. for moisture sensitivity level (msl), please see device information page for isl23325 . for more information on msl please see techbrief tb363 .
isl23325 4 fn7870.0 june 21, 2011 absolute maximum rating s thermal information supply voltage range v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v v logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v voltage on any dcp terminal pin . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v voltage on any digital pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v wiper current i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . .4.5kv cdm model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . . . . . . . . 1kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 300v latch up (tested per jesd-78b; class 2, level a) . . . . 100ma @ +125c thermal resistance (typical) ja (c/w) jc (c/w) 14 ld tssop package (notes 6, 7) . . . . . . 112 40 16 ld tqfn package (notes 6, 7) . . . . . . 110 64 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c v cc supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7v to 5.5v v logic supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2v to 5.5v dcp terminal voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to v cc max wiper current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3ma caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 7. for jc , the ?case temp? location is the center top of the package. analog specifications v cc = 2.7v to 5.5v, v logic = 1.2v to 5.5v over recommended operating conditions unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +125c. symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units r total rh to rl resistance w option 10 k ? u option 50 k ? t option 100 k ? rh to rl resistance tolerance -20 2 +20 % end-to-end temperature coefficient w option 125 ppm/c u option 65 ppm/c t option 45 ppm/c v rh , v rl dcp terminal voltage v rh or v rl to gnd 0v cc v rw wiper resistance rh - floating, v rl = 0v, force i w current to the wiper, i w = (v cc - v rl )/r total, v cc = 2.7v to 5.5v 70 200 ? v cc = 1.7v 580 ? c h /c l /c w terminal capacitance see ?dcp macro model? on page 9 32/32/32 pf i lkgdcp leakage on dcp pins voltage at pin from gnd to v cc -0.4 <0.1 0.4 a noise resistor noise density wiper at middle point, w option 16 nv/ hz wiper at middle point, u option 49 nv/ hz wiper at middle point, t option 61 nv/ hz feed thru digital feed-through from bus to wiper wiper at middle point -65 db psrr power supply reject ratio wiper output change if v cc change 10%; wiper at middle point -75 db
isl23325 5 fn7870.0 june 21, 2011 voltage divider mode (0v @ rl; v cc @ rh; measured at rw, unloaded) inl (note 13) integral non-linearity, guaranteed monotonic w option -1.0 0.5 +1.0 lsb (note 9) u, t option -0.5 0.15 +0.5 lsb (note 9) dnl (note 12) differential non-linearity, guaranteed monotonic w option -1 0.4 +1 lsb (note 9) u, t option -0.4 0.1 +0.4 lsb (note 9) fserror full-scale error w option -5 -2 0 lsb (note 9) u, t option -2 -0.5 0 lsb (note 9) zserror (note 10) zero-scale error w option 0 2 5 lsb (note 9) u, t option 0 0.4 2 lsb (note 9) vmatch (note 22) dcp to dcp matching dcps at same tap position, same voltage at all rh terminals, and same voltage at all rl terminals -2 0.5 2 lsb (note 9) tc v (notes 14) ratiometric temperature coefficient w option, wiper register set to 80 hex 8 ppm/c u option, wiper register set to 80 hex 4 ppm/c t option, wiper register set to 80 hex 2.3 ppm/c t ls_settling large signal wiper settling time from code 0 to ff hex, measured from 0 to 1 lsb settling of the wiper 300 ns f cutoff -3db cutoff frequency wiper at middle point w option 1200 khz wiper at middle point u option 250 khz wiper at middle point t option 120 khz rheostat mode (measurements between rw and rl pins with rh not connected, or between rw and rh with rl not connected) r inl (note 18) integral non-linearity, guaranteed monotonic w option; v cc = 2.7v to 5.5v -2.0 1 +2.0 mi (note 15) w option; v cc = 1.7v 10.5 mi (note 15) u, t option; v cc = 2.7v to 5.5v -1.0 0.3 +1.0 mi (note 15) u, t option; v cc = 1.7v 2.1 mi (note 15) r dnl (note 17) differential non-linearity, guaranteed monotonic w option; v cc = 2.7v to 5.5v -1 0.4 +1 mi (note 15) w option; v cc = 1.7v 0.6 mi (note 15) u, t option; v cc = 2.7v to 5.5v -0.5 0.15 +0.5 mi (note 15) u, t option; v cc = 1.7v 0.35 mi (note 15) analog specifications v cc = 2.7v to 5.5v, v logic = 1.2v to 5.5v over recommended operating conditions unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +125c. (continued) symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units
isl23325 6 fn7870.0 june 21, 2011 r offset (note 16) offset, wiper at 0 position w option; v cc = 2.7v to 5.5v 0 3 5.5 mi (note 15) w option; v cc = 1.7v 6.3 mi (note 15) u, t option; v cc = 2.7v to 5.5v 0 0.5 2 mi (note 15) u, t option; v cc = 1.7v 1.1 mi (note 15) rmatch (note 23) dcp to dcp matching any two dcps at the same tap position with the same terminal voltages -2 2 lsb (note 9) tcr (note 19) resistance temperature coefficient w option; wiper register set between 32 hex and ff hex 170 ppm/c u option; wiper register set between 32 hex and ff hex 80 ppm/c t option; wiper register set between 32 hex and ff hex 50 ppm/c analog specifications v cc = 2.7v to 5.5v, v logic = 1.2v to 5.5v over recommended operating conditions unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +125c. (continued) symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units operating specifications v cc = 2.7v to 5.5v, v logic = 1.2v to 5.5v over recommended operat ing conditions unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +125c. symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units i logic v logic supply current (write/read) v logic = 5.5v, v cc = 5.5v, f scl = 400khz (for i 2 c active read and write) 200 a v logic = 1.2v, v cc = 1.7v, f scl = 400khz (for i 2 c active read and write) 5 a i cc v cc supply current (write/read) v logic = 5.5v, v cc = 5.5v 18 a v logic = 1.2v, v cc = 1.7v 10 a i logic sb v logic standby current v logic = v cc = 5.5v, i 2 c interface in standby 1 a v logic = 1.2v, v cc = 1.7v, i 2 c interface in standby 0.5 a i cc sb v cc standby current v logic = v cc = 5.5v, i 2 c interface in standby 2 a v logic = 1.2v, v cc = 1.7v, i 2 c interface in standby 1.2 a i logic shdn v logic shutdown current v logic = v cc = 5.5v, i 2 c interface in standby 1 a v logic = 1.2v, v cc = 1.7v, i 2 c interface in standby 0.5 a i cc shdn v cc shutdown current v logic = v cc = 5.5v, i 2 c interface in standby 2 a v logic = 1.2v, v cc = 1.7v, i 2 c interface in standby 1.2 a i lkgdig leakage current, at pins a0, a1, a2, sda, scl voltage at pin from gnd to v logic -0.4 <0.1 0.4 a
isl23325 7 fn7870.0 june 21, 2011 t dcp wiper response time scl rising edge of the acknowledge bit after data byte to wiper new position (changes from 10% to 90% fs) w, u, t options specified top to bottom 0.4 s 1.5 s 3.5 s tshdnrec dcp recall time from shutdown mode scl rising edge of the acknowledge bit after acr data byte to wiper recalled position and rh connection 1.5 s v cc, v logic ramp (note 21) v cc , v logic ramp rate ramp monotonic at any level 0.01 50 v/ms operating specifications v cc = 2.7v to 5.5v, v logic = 1.2v to 5.5v over recommended operat ing conditions unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +125c. (continued) symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units serial interface specification for scl, sda, a0, a1, a2 unless otherwise noted. symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units v il input low voltage -0.3 0.3 x v logic v v ih input high voltage 0.7 x v logic v logic + 0.3 v hysteresis sda and scl input buffer hysteresis v logic > 2v 0.05 x v logic v v logic < 2v 0.1 x v logic v v ol sda output buffer low voltage i ol = 3ma, v logic > 2v 0 0.4 v i ol = 1.5ma, v logic < 2v 0.2 x v logic v c pin sda, scl pin capacitance 10 pf f scl scl frequency 400 khz t sp pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v logic , until sda exits the 30% to 70% of v logic window 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v logic during a stop condition, to sda crossing 70% of v logic during the following start condition 1300 ns t low clock low time measured at the 30% of v logic crossing 1300 ns t high clock high time measured at the 70% of v logic crossing 600 ns t su:sta start condition set-up time scl rising edge to sda falling edge; both crossing 70% of v logic 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v logic to scl falling edge crossing 70% of v logic 600 ns t su:dat input data set-up time from sda exiting the 30% to 70% of v logic window, to scl rising edge crossing 30% of v logic 100 ns
isl23325 8 fn7870.0 june 21, 2011 t hd:dat input data hold time from scl falling edge crossing 70% of v logic to sda entering the 30% to 70% of v logic window 0ns t su:sto stop condition set-up time from scl rising edge crossing 70% of v logic , to sda rising edge crossing 30% of v logic 600 ns t hd:sto stop condition hold time for read or write from sda rising edge to scl falling edge; both crossing 70% of v logic 1300 ns t dh output data hold time from scl falling edge crossing 30% of v logic , until sda enters the 30% to 70% of v logic window. i ol =3ma,v logic > 2v. i ol = 0.5ma, v logic < 2v 0ns t r sda and scl rise time from 30% to 70% of v logic 20 + 0.1 x cb 250 ns t f sda and scl fall time from 70% to 30% of v logic 20 + 0.1 x cb 250 ns cb capacitive loading of sda or scl total on-chip and off-chip 10 400 pf t su:a a2, a1, a0 setup time before start condition 600 ns t hd:a a2, a1, a0 hold time after stop condition 600 ns notes: 8. typical values are for t a = +25c and 3.3v supply voltages. 9. lsb = [v(rw) 255 ? v(rw) 0 ] / 255. v(rw) 255 and v(rw) 0 are v(rw) for the dcp register set to ff hex and 00 hex respectively. lsb is the incremental voltage when changing from one tap to an adjacent tap. 10. zs error = v(rw) 0 / lsb. 11. fs error = [v(rw) 255 ? v cc ] / lsb. 12. dnl = [v(rw) i ? v(rw) i-1 ] / lsb-1, for i = 1 to 255. i is the dcp register setting. 13. inl = [v(rw) i ? i ? lsb ? v(rw) 0 ]/lsb for i = 1 to 255 14. for i = 16 to 255 decimal, t = -40c to +125c. max( ) is the maximum value of the wiper voltage and min( ) is the minimum value of the wiper voltage over the temperature range. 15. mi = | rw 255 ? rw 0 | / 255. mi is a minimum increment. rw 255 and rw 0 are the measured resistances for the dcp register set to ff hex and 00 hex respectively. 16. roffset = rw 0 / mi, when measuring between rw and rl. roffset = rw 255 / mi, when measuring between rw and rh. 17. rdnl = (rw i ? rw i-1 ) / mi -1, for i = 16 to 255. 18. rinl = [rw i ? (mi ? i) ? rw 0 ] / mi, for i = 16 to 255. 19. for i = 16 to 255, t = -40c to +125c. max( ) is the maximum value of the resistance and min( ) is the minimum value of the resistance over the temperature range. 20. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 21. it is preferable to ramp up both the v logic and the v cc supplies at the same time. if this is not possible, it is recommended to ramp-up the v logic first followed by the v cc . 22. vmatch = [v(rwx)i - v(rwy)i]/lsb, for i = 1 to 255, x = 0 to 1 and y = 0 to 1. 23. rmatch = (rwi,x - rwi,y)/mi, for i = 1 to 255 , x = 0 to 1 and y = 0 to 1. serial interface specification for scl, sda, a0, a1, a2 unless otherwise noted. (continued) symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units tc v max v rw () i () min v rw () i () ? vrw i +25c () () ----------------------------------------------------------------------------- - 10 6 +165c --------------------- = tc r max ri () min ri () ? [] ri +25c () ------------------------------------------------------ - 10 6 +165c --------------------- =
isl23325 9 fn7870.0 june 21, 2011 dcp macro model timing diagrams sda vs scl timing a0, a1, and a2 pin timing 32pf rh r total c h 32pf c w c l 32pf rw rl t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r t sp t hd:a scl sda a0, a1, a2 t su:a clk 1 start stop
isl23325 10 fn7870.0 june 21, 2011 typical performance curves figure 3. 10k ? dnl vs tap position, v cc = 3.3v, +25c figure 4. 50k ? dnl vs tap position, v cc = 3.3v, +25c figure 5. 10k ? inl vs tap position, v cc = 3.3v, +25c figure 6. 50k ? inl vs tap position, v cc = 3.3v, +25c figure 7. 10k ? rdnl vs tap position, v cc = 3.3v, +25c figure 8. 50k ? rdnl vs tap position, v cc = 3.3v, +25c -0.4 -0.2 0 0.2 0.4 0 64 128 192 256 d n l ( l s b ) tap position (decimal) -0.08 -0.04 0.00 0.04 0.08 0 64 128 192 256 d n l ( l s b ) tap position (decimal) -0.80 -0.40 0.00 0.40 0.80 0 64 128 192 256 i n l ( l s b ) tap position (decimal) -0.16 -0.08 0.00 0.08 0.16 0 64 128 192 256 i n l ( l s b ) tap position (decimal) -0.40 -0.20 0.00 0.20 0.40 0 64 128 192 256 r d n l ( m i ) tap position (decimal) -0.10 -0.05 0.00 0.05 0.10 0 64 128 192 256 r d n l ( m i ) tap position (decimal)
isl23325 11 fn7870.0 june 21, 2011 figure 9. 10k ? rinl vs tap position, v cc = 3.3v, +25c figure 10. 50k ? rinl vs tap position, v cc = 3.3v, +25c figure 11. 10k ? wiper resistance vs tap position, v cc = 3.3v figure 12. 50k ? wiper resistance vs tap position, v cc = 3.3v figure 13. 10k ? tcv vs tap position, v cc = 3.3v figure 14. 50k ? tcv vs tap position, v cc = 3.3v typical performance curves (continued) -0.80 -0.40 0.00 0.40 0.80 0 64 128 192 256 r i n l ( m i ) tap position (decimal) -0.14 -0.07 0.00 0.07 0.14 0 64 128 192 256 r i n l ( m i ) tap position (decimal) 0 20 40 60 80 100 0 64 128 192 256 w i p e r r e s i s t a n c e ( ) tap position (decimal) +125c -40c +25c 0 20 40 60 80 100 120 0 64 128 192 256 w i p e r r e s i s t a n c e ( ) tap position (decimal) +125c -40c +25c 0 100 200 300 400 15 63 111 159 207 255 t c v ( p p m / c ) tap position (decimal) 0 20 40 60 80 15 63 111 159 207 255 t c v ( p p m / c ) tap position (decimal)
isl23325 12 fn7870.0 june 21, 2011 figure 15. 10k ? tcr vs tap position figure 16. 50k ? tcr vs tap position, v cc = 3.3v figure 17. 100k ? tcv vs tap position, v cc = 3.3v figure 18. 100k ? tcr vs tap position, v cc = 3.3v figure 19. wiper digital feed-through figure 20. wiper transition glitch typical performance curves (continued) 0 200 400 600 800 15 63 111 159 207 255 t c r ( p p m / c ) tap position (decimal) 0 50 100 150 200 250 15 63 111 159 207 255 t c r ( p p m / c ) tap position (decimal) 0 10 20 30 40 50 15 63 111 159 207 255 t c v ( p p m / c ) tap position (decimal) 0 30 60 90 120 150 15 63 111 159 207 255 t c r ( p p m / c ) tap position (decimal) scl clock rw pin ch1: 1v/div, 1s/div ch2: 10mv/div, 1s/div ? ch1: 20mv/div, 2s/div ch2: 2v/div, 2s/div scl wiper 9th clk of the data byte (ack)
isl23325 13 fn7870.0 june 21, 2011 functional pin descriptions potentiometers pins rh i and rl i the high (rhi, i = 0, 1) and low (rli, i = 0,1) terminals of the isl23325 are equivalent to the fi xed terminals of a mechanical potentiometer. rhi and rli are referenced to the relative position of the wiper and not the voltage potential on the terminals. with wri set to 255 decimal, the wiper wi ll be closest to rhi, and with the wr set to 0, the wiper is closest to rli. rw i rwi (i = 0,1) is the wiper terminal, and it is equivalent to the movable terminal of a mechanical potentiometer. the position of the wiper within the array is determined by the wri register. v cc power terminal for the potentiometer section analog power source. can be any value needed to support voltage range of dcp pins, from 1.7v to 5.5v, independent of the v logic voltage. bus interface pins serial data input/output (sda) the sda is a bi-directional serial data input/output pin for i 2 c interface. it receives device address, wiper address and data from an i 2 c external master device at th e rising edge of the serial clock scl, and it shifts out data after each falling edge of the serial clock. sda requires an external pull-up resistor, since it is an open drain input/output. figure 21. wiper large signal settling time figure 22. power-on start-up in voltage divider mode figure 23. 10k ? -3db cut off frequency figure 24. standby current vs temperature typical performance curves (continued) ? 9th clock of the data byte (ack) 1v/div 0.2s/div scl wiper ? 0.5v/div 20s/div v cc wiper ? 0.5v/div, 0.2s/div -3db frequency = 1.4mhz at middle tap ch1: rh terminal ch2: rw terminal 0 0.2 0.4 0.6 0.8 1.0 1.8 -40 -15 10 35 60 85 110 s t a n d b y c u r r e n t i c c ( a ) temperature (c) v cc = 5.5v, v logic = 5.5v v cc = 1.7v, v logic = 1.2v 1.6 1.4 1.2
isl23325 14 fn7870.0 june 21, 2011 serial clock (scl) this input is the serial clock of the i 2 c serial interface. scl requires an external pull-up resistor, since a master is an open drain output. device address (a2, a1, a0) the address inputs are used to se t the least significant 3 bits of the 7-bit i 2 c interface slave address. a match in the slave address serial data stream must match with the address input pins in order to initiate comm unication with the isl23325. a maximum of eight isl23325 devices may occupy the i 2 c serial bus (see table 3). v logic digital power source for the logic control section. it supplies an internal level translator for 1.2v to 5.5v serial bus operation. use the same supply as the i 2 c logic source. principles of operation the isl23325 is an integrated circ uit incorporating two dcps with its associated registers and an i 2 c serial interface providing direct communication between a host and the potentiometer. the resistor array is comprised of individual resistors connected in series. at either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. the electronic switches on the device operate in a ?make-before-break? mode when the wiper changes tap positions. voltage at any dcp pins, rhi, rli or rwi, should not exceed v cc level at any conditions during power-up and normal operation. the v logic pin is the terminal for the logic control digital power source. it should use the same supply as the i 2 c logic source which allows reliable communication with a wide range of microcontrollers and is independent from the v cc level. this is extremely important in systems where the master supply has lower levels than dcp analog supply. dcp description each dcp is implemented with a co mbination of resistor elements and cmos switches. the physical en ds of each dcp are equivalent to the fixed terminals of a mechanical potentiometer (rhi and rli pins). the rwi pin of the dcp is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. the position of the wiper terminal within the dcp is controlled by an 8-bit volatile wiper register (wri). when the wri of a dcp contains all zeroes (wri [7:0] = 00h), its wiper terminal (rwi) is closest to its ?low? terminal (rli). when the wri register of a dcp contains all ones (wri [7:0] = ffh), its wiper terminal (rwi) is closest to its ?high? termin al (rhi). as the value of the wri increases from all zeroes (0) to all ones (255 decimal), the wiper moves monotonically from the position closest to rli to the position closest to rhi. at the same time, the resistance between rwi and rli increases monotonically, while the resistance between rhi and rwi decreases monotonically. while the isl23325 is being po wered up, both wr0 and wr1 are reset to 80h (128 decimal), which positions rwi at the center between rli and rhi. the wri can be read or written to directly using the i 2 c serial interface as described in the following sections. memory description the isl23325 contains three volatile 8-bit registers: wiper register wr0, wiper register wr1, and access control register (acr). memory map of the isl23325 is shown in table 1. the wiper register wr0 at address 0, contains current wiper position of dcp0; the wiper register wr1 at address 1 contains current wiper position of dcp1. the access control register (acr) at address 10h contains information and control bits described in table 2. shutdown function the shdn bit (acr[6]) disables or enables shutdown mode for all dcp channels simultaneously. when this bit is 0, i.e., dcp is forced to end-to-end open circuit and rw is connected to rl through a 2k ? serial resistor as shown in figure 25. default value of the shdn bit is 1. when the device enters shutdown, all current dcp wr settings are maintained. when the device exits shutdown, the wipers will return to the previous wr settings after a short settling time (see figure 26). in shutdown mode, if there is a glitch on the power supply which causes it to drop below 1.3v for more than 0.2 to 0.4s, the wipers will be reset to their mid position. this is done to avoid an undefined state at the wiper outputs. table 1. memory map address (hex) volatile register name default setting (hex) 10 acr 40 1wr1 80 0wr0 80 table 2. access control register (acr) bit # 76543210 name/ value 0shdn 000000 figure 25. dcp connection in shutdown mode 2k ? rw rl rh
isl23325 15 fn7870.0 june 21, 2011 i 2 c serial interface the isl23325 supports an i 2 c bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the re ceiving device as the receiver. the device controlling the transf er is a master and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and receive operations. therefore, the isl23325 operates as a slave device in all applications. all communication over the i 2 c interface is conducted by sending the msb of each byte of data first. protocol conventions data states on the sda line mu st change only during scl low periods. sda state changes during scl high are reserved for indicating start and stop conditions (see figure 27). on power-up of the isl23325, the sda pin is in the input mode. all i 2 c interface operations must be gin with a start condition, which is a high-to-low transition of sda while scl is high. the isl23325 continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 27 ). a start condition is ignored during the power-up of the device. all i 2 c interface operations must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 27). a stop condition at the end of a read operation or at the end of a write operation places the device in its standby mode. an ack (acknowledge) is a software convention used to indicate a successful data transfer. the tr ansmitting device, either master or slave, releases the sda bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data (see figure 28). the isl23325 responds with an ac k after recognit ion of a start condition followed by a valid iden tification byte, and once again after successful receipt of an address byte. the isl23325 also responds with an ack after rece iving a data byte of a write operation. the master must respond with an ack after receiving a data byte of a read operation. a valid identification byte contains 1010 as the four msbs, and the following three bits are matching the logic values present at pins a2, a1 and a0. the lsb is the read/write bit. its value is ?1? for a read operation and ?0? for a write operation (see table 3). table 3. identification byte format figure 26. shutdown mode wiper response power-up user programmed mid scale = 80h shdn activated shdn released after shdn wiper voltage, v rw (v) shdn mode time (s) wiper restore to the original position 0 1010a2a1a0r/w (msb) (lsb) logic values at pins a2, a1 and a0 respectively sda scl start data data stop stable change data stable figure 27. valid data changes, start and stop conditions
isl23325 16 fn7870.0 june 21, 2011 write operation a write operation requires a start condition, followed by a valid identification byte, a valid address byte, a data byte, and a stop condition. after each of the three bytes, the isl23325 responds with an ack. the data is transferred from i 2 c block to the corresponding register at the 9th clock of the data byte and the device enters its standby state (see figures 28 and 29). it is possible to perform a sequential write to all dcp channels via a single write operation. the command is initiated by sending an additional data byte after the first data byte instead of sending a stop condition. read operation a read operation consists of a th ree byte instruction followed by one or more data bytes (see figure 30). the master initiates the operation issuing the following sequence: a start, the identification byte with the r/w bit set to ?0?, an address byte, a second start, and a second iden tification byte with the r/w bit set to ?1?. after each of the three bytes, the isl23325 responds with an ack; then the isl23325 transmits data byte. the master terminates the read operation issuing a nack (ack ) and a stop condition following the last bit of the last data byte (see figure 30). sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance figure 28. acknowledge response from receiver s t a r t s t o p identification byte address byte data byte a c k signals from the master signals from the slave a c k 10 1 00 a c k write signal at sda 000 a0 a1 figure 29. byte write sequence a2 signals from the master signals from the slave signal at sda s t a r t identification byte with r/w = 0 address byte a c k a c k 10 1 00 s t o p a c k 1 identification byte with r/w = 1 a c k s t a r t last read data byte first read data byte a c k 000 a0 a1 a0 a1 figure 30. read sequence a c k a2 a2 101 0 read
isl23325 17 fn7870.0 june 21, 2011 applications information v logic requirements v logic should be powered continuously during normal operation. in a case where turning v logic off is necessary, it is recommended to ground the v logic pin of the isl23325. grounding the v logic pin or both v logic and v cc does not affect other devices on the same bus. it is good practice to put a 1f cap in parallel to 0.1f as close to the v logic pin as possible. v cc requirements and placement it is recommended to put a 1f capacitor in parallel with 0.1f decoupling capacitor close to the v cc pin. wiper transition when stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/unders hoot, resulting from the sudden transition from a very low impe dance ?make? to a much higher impedance ?break? within a short period of time (<1s). there are several code transitions such as 0fh to 10h, 1fh to 20h,..., efh to ffh, which have higher transient glitch. note, that all switching transients will settle well within the settling time as stated in the datasheet. a sm all capacitor can be added externally to reduce the amplitude of these voltage transients. however, that will also reduce the useful bandwidth of the circuit, thus may not be a good solution for some applications. it may be a good idea, in that case, to use fast amplifiers in a signal chain for fast recovery.
isl23325 18 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7870.0 june 21, 2011 for additional products, see www.intersil.com/product_tree revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. products intersil corporation is a leader in the desi gn and manufacture of high-performance an alog semiconductors. the company's product s address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. in tersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl23325 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php date revision change 6/21/11 fn7870.0 initial release.
isl23325 19 fn7870.0 june 21, 2011 package outline drawing m14.173 14 lead thin shrink small outline package (tssop) rev 3, 10/09 detail "x" side view typical recommended land pattern top view b a 17 8 14 c plane seating 0.10 c 0.10 c b a h pin #1 i.d. mark 5.00 0.10 4.40 0.10 0.25 +0.05/-0.06 6.40 0.20 c b a 0.05 0-8 gauge plane see 0.90 +0.15/-0.10 0.60 0.15 0.09-0.20 5 2 3 1 3 1.00 ref 0.65 1.20 max 0.25 0.05 min 0.15 max (1.45) (5.65) (0.65 typ) (0.35 typ) detail "x" 1. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 per side. 3. dimensions are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m-1994. 5. dimension does not include dambar protrusion. allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. minimum space between protrusion and adjacent lead is 0.07mm. 6. dimension in ( ) are for reference only. 7. conforms to jedec mo-153, variation ab-1. notes: end view
isl23325 20 fn7870.0 june 21, 2011 ultra thin quad flat no-lead plastic package (utqfn) 6 b e a d 0.10 c 2x c 0.05 c a 0.10 c a1 seating plane index area 2 1 n top view bottom view side view nx (b) section "c-c" e cc 5 c l terminal tip (a1) l 0.10 c 2x e l1 nx l 2 1 0.10 m c a b 0.05 m c 5 nx b (datum b) (datum a) pin #1 id 16x 3.00 1.40 2.20 0.40 0.50 0.20 0.40 0.20 0.90 1.40 1.80 land pattern 10 k l16.2.6x1.8a 16 lead ultra thin quad flat no-lead plastic package symbol millimeters notes min nominal max a 0.45 0.50 0.55 - a1 - - 0.05 - a3 0.127 ref - b 0.15 0.20 0.25 5 d 2.55 2.60 2.65 - e 1.75 1.80 1.85 - e 0.40 bsc - k0.15 - - - l 0.35 0.40 0.45 - l1 0.45 0.50 0.55 - n162 nd 4 3 ne 4 3 0-12 4 rev. 5 2/09 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on d and e side, respectively. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. maximum package warpage is 0.05mm. 8. maximum allowable burrs is 0.076mm in all directions. 9. jedec reference mo-255. 10. for additional information, to assist with the pcb land pattern design effort, see intersil technical brief tb389.

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